[Omp] OpenMP spec 2.5 seems to have incorrect flush example on page 12

[Greg Bronevetsky]

> This is clever and it is essentially what hardware caches do:
> if they are not write-through, they keep a bit to tell that
> cached cell is "dirty" and needs to be flushed when the
> cached cell is evacuated for new content.
> 
   That was exactly the idea.

> But your assessment that the overhead compared to sequential
> performance is pretty small is not correct in my view. It
> means that the compiler has to introduce software managed
> dirty-bits for every shared memory location that is written.
> The additional control flow "IF(dirty-X) X=r" can turn out
> to be quite costly.
> 
   That's not quite true. The dirty bits are only required for locations
that you want to registerize, which isn't that large a number, definitely
<=128. All memory besides registers already offers this dirty bit
functionality. I guess, more generally, you can think of this as compiling
threaded code for an incoherent cache. Intuitively you can see that it
won't be pretty.

                             Greg Bronevetsky