OpenMP® ARB adds new member Samsung
The OpenMP Architecture Review Board (ARB) today announced that Samsung has joined the board.
SiFive joins the OpenMP® effort
SiFive joins the OpenMP Architecture Review Board (ARB), a group of leading hardware vendors, software vendors and research organizations, in creating the standard for the most popular shared-memory parallel programming model in use today.
OpenMP ARB Releases Technical Report 11
The OpenMP® Architecture Review Board (ARB) has released Technical Report 11, the first preview of the future version 6.0 of the OpenMP API and version 5.2.1 of the collection of programming examples.
OpenMP ARB Appoints Jack Dongarra to its Board of Directors
The OpenMP ARB welcomes Jack Dongarra to its Board of Directors. His insights and guidance will greatly benefit the Board.
The Pawsey Supercomputer Research Centre joins the OpenMP effort
At Pawsey, we are confident that OpenMP will be instrumental in addressing future portability and scalability challenges.
OpenMP ARB Releases OpenMP 5.2
Version 5.2 refactors the OpenMP specification to improve consistency of its syntax and semantic restrictions.
OpenMP ARB Releases Technical Report 10
The OpenMP Architecture Review Board (ARB) has released Technical Report 10, the preview for the future version 5.2 of the OpenMP API.
CSC Finland Joins the OpenMP Effort
"At CSC, we expect that with the pre-exascale EuroHPC LUMI supercomputer, OpenMP will play an important role in preparing our applications for the heterogeneous architecture and the exascale era." George Markomanolis, Lead HPC Scientist at CSC
Mentor Graphics and the University of Basel join the OpenMP effort
“We are delighted to welcome Mentor and the University of Basel as our newest members”, says Michael Klemm, CEO of the OpenMP ARB, “Both are very active in the open source and scientific community, and underline the relevance of the OpenMP API in the HPC community.”
OpenMP ARB releases OpenMP 5.1 with vital usability enhancements
While the primary focus has been enhancements, clarifications and corrections to the 5.0 specification, several useful new features have been added such as support for interoperability with lower level APIs like CUDA and HIP.